In modern integrated circuits, waste heat is produced due to the presence of a very high number of individual circuit elements, such as field effect transistors in the form of CMOS, NMOS, PMOS elements, resistors, capacitors, and the like, or due to the presence of high power components operating at elevated current levels. Typically, feature sizes of these circuit elements are continuously decreased with the introduction of every new circuit generation to provide currently available integrated circuits formed by volume production techniques with critical dimensions of 50 nm or less in the small signal regime and having an improved degree of performance in terms of speed and/or power consumption. On the other hand, power transistors, IGBT, and the like are used in high-power applications or in circuit portions of combined small signal/high-power devices, which operate at operating currents of several 100 A and higher. A reduction in size of transistors is an important aspect in steadily improving device performance of complex integrated circuits, such as CPUs. The reduction in size is commonly associated with an increased switching speed, thereby enhancing signal processing performance at transistor level.
In addition to the large number of transistor elements a plurality of passive circuit elements, such as capacitors, resistors, interconnect structures and the like are typically formed in integrated circuits as required by the basic circuit layout. Due to the decreased dimensions of the active circuit elements, not only performance of the individual transistor elements may be increased, but also their packing density may be improved, thereby providing the potential for incorporating increased functionality into a given chip area. For this reason, highly complex circuits have been developed, which may include different types of circuits, such as analog circuits, digital circuits, power circuits and the like, thereby providing entire systems on a single chip (SoC).
The increased packing density of integrated circuits resulting from the reduced device dimensions may also be accompanied by reduced switching speeds of the individual transistors in complex logic circuitry, thereby frequently contributing to increased power consumption in MOS circuits, since the reduced switching speeds allow the operation of the transistors at higher switching frequencies, which in turn increases the dynamic power consumption of the entire device. Furthermore, usually increased switching speed of advanced transistors is associated with very thin gate dielectrics, which contributes to increased static power consumption. Therefore, in sophisticated applications using densely packed integrated circuits the heat generation may reach extremely high values due to the dynamic losses caused by the high operating frequency in combination with a significant static power consumption of highly scaled transistor devices owing to increased leakage currents that may stem from extremely thin gate dielectrics, short channel effects, and the like. Similarly, in power applications the reduction of size of the power devices also results in increased switching times and high current density. Therefore, great efforts are being made in order to reduce overall power consumption by restricting the usage of high performance transistors, which usually cause higher heat generation, to performance critical signal paths in the circuit design, while using less critical devices in a other circuit areas. Moreover, appropriate mechanisms may be implemented to operate certain circuit portions “on demand” and control local or global operating conditions depending on the thermal situation in the semiconductor die.
The heat generated during the operation of the internal circuit elements is typically dissipated via the substrate material or the complex metallization system including highly conductive metals and sophisticated dielectric materials, depending on the overall configuration of the semiconductor device, the package accommodating the semiconductor device and the contact regime for connecting the metallization system to the wiring system of the package. Finally, the internally generated heat has to be transferred to the package and to an external cooling system connected to the package. Thus, a wide variety of cooling systems have been developed with complex passive architectures, such as specifically designed heat sinks and heat pipes, and also expensive active cooling devices, for instance in the form of fans, water cooling systems, Peltier elements, and the like. With the quest for high performance of complex semiconductor devices, the corresponding power consumption of semiconductor devices, such as microprocessors, have reached the 100 Watt range, while the shrinking technology ground rules have resulted in increased thermal density of these semiconductor devices, since continuously more transistors are packed into a smaller die region. Since external heat management systems, i.e. systems, which may be operated on the basis of the internal thermal state of the semiconductor device, may not enable a reliable estimation of the die internal temperature distribution due to the delayed thermal response of the package of the semiconductor device and the possibly insufficient spatial temperature resolution of device internal temperature monitoring systems, respective external cooling systems may have to be designed so as to take into consideration these restrictions and to provide for sufficient operational margins with respect to heat control unless a certain risk of overheating and thus possibly damaging specific critical circuit portions may be caused.
The problem of imbalanced heat dissipation capabilities of an external cooling system with respect to their waste heat produced by a complex semiconductor device may even be exaggerated in situations, in which so-called hot spots may be present in the semiconductor device, which may not directly be similarly coupled to an efficient heat sink. That is, frequently the design of complex integrated circuits requires the provision of fast switching transistors in critical signal paths to be implemented at certain device areas, without having the possibility to appropriately similarly connect these critical circuit areas with high-performance heat dissipation areas. In this case, during operation local high-temperature areas are generated with less than desired heat spreading functionality, thereby requiring operation of the device such that a critical temperature in these hot spots will not be exceeded for a given heat dissipation capability of an external cooling mechanism. In particular with the introduction of sophisticated low-k dielectric based metallization systems in complex semiconductor devices and/or with the application of ever increasing current densities in active semiconductor devices, such as power MOS transistors, and the like, the lateral thermal conductivity capabilities of the semiconductor device itself may not be sufficient so as to allow a sufficient lateral heat distribution in order to more fully exploit the heat dissipation capabilities of an external cooling system.
Consequently, since a substantially linear increase of the total thermal power margins may be observed with the scaling of the device dimensions, while, on the other hand, the power density may over-proportionally increase, a corresponding adaptation of heat dissipation systems may be required, in particular for initially transferring heat from the actual semiconductor device to a carrier substrate or package.
FIG. 1A schematically illustrates a conventional semiconductor device 150 in a substantially “packaged” state, in which a semiconductor chip 120 is attached to an appropriate carrier substrate 110, which may represent any appropriate carrier material for receiving the semiconductor chip 120 and to provide an infrastructure of electrical connections so as to allow the routing of signals and power from and to the semiconductor chip 120. In the conventional example of FIG. 1A the semiconductor chip 120 is attached to an appropriately configured surface 110A of the substrate 110 by means of a direct bond mechanism, in which solder balls 121 or any other appropriate contact structure connect to a complementary contact structure (not shown) of the carrier 110. In this case, the contact elements 121, which are frequently provided in the form of solder bumps, ensure mechanical, electrical and thermal contact to the carrier substrate 110, which, however, for high-performance devices may not be sufficient for transferring a desired amount of heat generated in the semiconductor chip 120 to the periphery. Therefore, in an attempt to additionally contribute to superior mechanical and thermal connectivity between the chip 120 and the carrier substrate 110 a filler material 160 is provided that enhances adhesion and/or thermal conductivity. Moreover, in sophisticated applications the heat dissipation capability obtained by connecting the chip 120 to the substrate 110 by means of the contact elements 121 and the filler material 160 may not be sufficient and additional heat transfer is accomplished by connecting a cooling element 140 to the chip 120 by means of an intermediate filler material 130 having superior heat conductivity characteristics. Although in this arrangement both main surfaces of the semiconductor chip 120 are used for heat dissipation it appears that in particular the characteristics of the filler materials 160 and 130 are of great importance with respect to the finally achieved heat dissipation capabilities of the device 150. Therefore, great efforts are being made in identifying appropriate filler materials having superior thermal conductivity, while still complying with the requirements imposed by volume production techniques in terms of costs and processability.
In many applications still other less sophisticated contact or packaging regimes are used, when a direct electrical connection of the contact structure of the semiconductor chip to an appropriate carrier substrate is not required. For example, high power semiconductor devices are frequently electrically connected by wire bonding, while the thermal and mechanical connection to a lead frame is accomplished by means of an appropriate filler material or glue material.
FIG. 1B schematically illustrates a corresponding configuration, in which the semiconductor device 150 is illustrated such that the semiconductor chip 120, which may comprise power elements, and the like, is mechanically attached to the surface 110A of the carrier substrate 110, provided in the form of a lead frame, by means of the filler material 160, which may thus represent any appropriate adhesive or glue material, while electrical contact of the chip 120 to the periphery may be accomplished by any appropriate contact structure formed on the opposite surface of the chip 120. In this case, the filler material 160 may require superior thermal conductivity, since the main part of the waste heat generated in the semiconductor chip 120 has to be transferred to the lead frame 110. For example, in particular in the configuration as shown in FIG. 1B well-established lead based solder materials are presently frequently used as the filler material 160, in particular when the semiconductor chip 120 represents a power circuit, while in less thermally demanding applications and also in small signal applications the filler material 160 is provided as an organic material, possibly including highly conductive metal particles, such as silver particles, and the like. Using an organic adhesive or glue material in combination with an appropriate metal species results in moderate thermal conductivity at low cost, may, however, not be compatible with thermal requirements of cutting edge semiconductor devices and future device generations in the small signal regime. On the other hand, in high-power applications the usage of lead based filler materials, such as lead/tin (Pb/Sn) based solder materials, ensures superior processability with respect to robust and well established process conditions, however, faces increasingly legal restrictions associated with the usage of lead in volume production products.
Therefore, a plurality of new materials has been proposed in order to meet the challenges of upcoming legal requirements and superior performance with respect to thermal connectivity and processability. For example, United States Patent Application Publication No. 2008/0202386 A1 (incorporated by reference) describes the use of self-orienting microplates in a thermally conductive material that is applied between the semiconductor chip and a carrier substrate as a thermal paste or adhesive. In some specific applications the material of the microplates comprises carbon and the form of graphite or graphene rolled into a fiber in order to obtain carbon nanotubes.
In view of the situation described above, the present disclosure relates to techniques for attaching a microstructure device chip to an appropriate carrier material while avoiding or at least reducing the effects of one or more of the problems identified above.